Field of the Invention
This technology relates to a level shifter which can be incorporated into a decoder for a NAND memory array.
Description of Related Art
With large capacity NAND flash designs, word lines of sufficient length to accommodate all the memory cells in the array have unacceptable capacitive loading. So the memory array is divided into multiple partitions with discretely decoded sets of word lines, such that the word lines in a partition have a lower, acceptable capacitive loading. The multiple decoders each include p-type and n-type transistors in series between a high voltage reference such as VDD and a low voltage reference such as ground or a negative voltage reference. FIG. 1 shows a large capacity memory divided into multiple partitions with respective word line decoders. The large capacity memory is divided into memory arrays or partitions 121, 122, and 123. The multiple memory arrays or partitions are accessed by respective word line decoders 111, 112, 113, 114, and 115. Because of the quantity of decoders in large capacity memories, the power performance of decoders has a significant impact on overall power performance.
Dynamic power consumption rises during switching actions of the p-type and n-type transistors in series between a high voltage reference such as VDD and a low voltage reference such as ground or a negative voltage reference. Example switching actions are from the p-type transistor being on and the n-type transistor being off, to the p-type transistor being off and the n-type transistor being on, and vice versa. During such switching actions, crossbar current flows directly between the high and low voltage references, through both the p-type transistor and the n-type transistor. Such crossbar current is a significant component of dynamic power consumption in the decoders.
U.S. Pat. No. 8,638,618 shows example decoders with level shifters that suffer from high levels of crossbar current flow during switching actions. FIG. 2 shows a level shifter with relatively high crossbar current, which can be used in a row decoder for a NAND flash memory. The level shifter includes stages 210, 220, and 230. Stage 210 includes voltage supply VDD and negative voltage supply VNP. Stage 210 includes two sets of p-type and n-type transistors coupled in series between VDD and VNP, with the drains coupled together, the source of the p-type transistor coupled to VDD, and the source of the n-type transistor coupled to VNP. The first set includes p-type transistor 211 and n-type transistor 213, where the drains are coupled to node N1. The second set includes p-type transistor 212 and n-type transistor 214, where the drains are coupled to node N2. The gate of n-type transistor 213 is coupled to node N2. The gate of n-type transistor 214 is coupled to node N1. Select signal SEL is received by the gate of p-type transistor 212 and its complement signal SELB is received by the gate of p-type transistor 211.
Stage 220 includes an inverter having an input coupled to node N2 and an output coupled to node N3.
Stage 230 has a positive voltage supply VPP with a higher magnitude than VDD in stage 210. Stage 230 includes an n-type pass transistor 231 having a gate coupled to VDD, and source and drain coupled to node N3 and output node generating signal SELH. Stage 230 also includes n-type depletion mode transistor 233 and p-type transistor 232 coupled in series between VPP and the output node generating signal SELH, where the drain of n-type depletion mode transistor 233 is coupled to VPP and the drain of p-type transistor 232 is coupled to the output node generating signal SELH, and the sources are coupled together. A gate of the drain of n-type depletion mode transistor 233 is coupled to the output node generating signal SELH. A gate of p-type transistor 232 receives signal SELB which is the complement of select signal SEL. Stage 230 also passes signal SELHB from node N2.
FIG. 3 shows voltage traces of the level shifter in FIG. 2, processing select block signals. The voltage traces include SEL 302, SELB 304, N1 306, N2 308, and SELH 310. FIG. 4 shows voltage traces of the level shifter in FIG. 2, processing de-select block signals. The voltage traces include SEL 402, SELB 404, N1 406, N2 408, and SELH 410.
In FIG. 3, during period T1, N2 308 is high at VLSP, and n-type transistor 213 is on due to N2 308 on the gate. During period T2, N2 308 falls from VLSP to VNP. During period T2 while the difference between N2 308 and VNP exceeds the turn-on voltage of n-type transistor 213, n-type transistor 213 is still fully on.
During period T1, SELB 304 changes from high to low. After SELB 304 changes to low during period T1, and while SELB 304 remains low during period T2, p-type transistor 211 is on due to SELB 304 on the gate.
Accordingly, during much of periods T1 and T2, both p-type transistor 211 and n-type transistor 213 are on, such that crossbar current flows between VDD and VNP. Such crossbar current occurs each time that a word line decoder selects a word line in each partition of a memory. It would be desirable to perform level shifting with reduced levels of crossbar current.